1. Field of the Invention
Generally, the present disclosure relates to the field of testing of integrated circuits, and, in particular, to measurements of alpha particle induced soft errors in semiconductor devices.
2. Description of the Related Art
The operation of integrated circuits such as, for example, memory circuits, logic circuits, field programmable gate arrays (FPGAs) and microprocessors, can be adversely affected by energetic particles from cosmic radiation or radioactive decay. In particular, energetic particle radiation can induce soft errors, which are non-destructive functional errors induced by the energetic particles. Energetic particle radiation can create charge carriers such as electrons and/or holes in a semiconductor material, such as silicon, which can change the logical state of circuit elements of an integrated circuit. For example, in the case of a memory cell, an impact of an energetic particle can change the data stored in the memory cell from a logical zero to a logical one, or from a logical one to a logical zero.
Energetic particles inducing soft errors in integrated circuits include, in particular, alpha particles emitted from radioactive impurities in materials nearby the sensitive volume of an integrated circuit, such as materials of packaging and/or solder bumps. Additionally, soft errors can be caused by particles from cosmic radiation or secondary particles created in the reaction of particles from cosmic radiation with the atmosphere, such as protons, electrons, positrons and/or neutrons.
For determining the influence of soft errors on the operation of an integrated circuit, measurements of a soft error rate (SER) at which soft errors occur may be performed.
One method of measuring a soft error rate occurring in the operation of an integrated circuit of a particular design is to test a large number of actual integrated circuits under typical use conditions for a relatively long period of time until enough soft errors have been accumulated to give a reasonably confident estimate of the soft error rate. This is denoted as “unaccelerated soft error rate testing.”
Unaccelerated soft error rate testing may have the advantage of being a direct measurement of the soft error rate occurring under typical use conditions. However, unaccelerated soft error rate testing can require the monitoring of a relatively large number of integrated circuits (hundreds or thousands) in parallel for relatively long periods of time (weeks or months). Therefore, unaccelerated soft error rate testing can be expensive and time consuming.
An alternative method for measuring a soft error rate is accelerated soft error rate testing. In accelerated soft error rate testing, integrated circuits are exposed to a specific radiation source whose intensity is much higher than the ambient levels of radiation the device would normally encounter. Accelerated soft error rate testing may allow obtaining useful data in a shorter amount of time than unaccelerated soft error rate testing, and a smaller number of integrated circuits may be required. Accelerated soft error rate testing has been employed, in particular, for measuring soft errors caused by alpha particle radiation.
Alpha particles are strongly ionizing. Therefore, alpha particles impinging on a semiconductor material in an integrated circuit, such as silicon, may create bursts of free electron-hole pairs, which may produce a current spike in the integrated circuit. These current spikes may be large enough to alter the data state on some circuits.
Since alpha particles typically have a relatively small penetration depth in matter, in accelerated testing of an alpha particle induced soft error rate, a surface of a device under test, such as an integrated circuit, is typically directly exposed to alpha radiation created by an alpha particle source without any intervening solid material and with a relatively small air gap. The device under test may be provided in a special package for alpha particle testing, wherein it is fixed and wire bonded within a well or cavity of the package.
An alpha particle source, for example, a radioactive source including a radioactive isotope that emits alpha particles, is provided adjacent the device under test. The device under test is operated, and errors occurring in the operation of the device are counted. For example, in the testing of an integrated circuit including a memory array, a known data pattern may be stored in the memory array, while the integrated circuit is exposed to the alpha particle source, and the stored pattern that is present in the memory array after the exposure to alpha particles may be compared with the known data pattern, wherein changes in the pattern are identified as errors.
Methods for accelerated testing for soft errors induced by alpha particles are described in JEDEC Standard JESD89A, “Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices,” published by JEDEC Solid State Technology Association 2001, 2500 Wilson Boulevard, Arlington, Va. 22201-3834.
Testing a sample of an integrated circuit, such as a static random access memory device (SRAM), may require scheduling a sample for a special backend processing that is performed for preparing the samples for wire bonding. This may require the use of a special mask that is employed for photolithography processes that are performed in the special backend processing. Typically, lots with a good yield are identified and treated as process of record (POR) lots.
The process of record lots are measured “inline” at wafer level for performing a functional testing. Good devices under test (DUTs) are selected, special wire bonding packages are designed, and finally the samples are built up as wire bonded samples. For the selected wire bonding package, sockets are ordered, and sample boards for testing by means of an automatic test equipment (ATE) are designed, ordered and checked. This may require relatively high resources of time, manpower and costs for development and delivery. Typically, a time delay between a first silicon test of a particular device and a final soft error rate test may be in a range from about 2 months to about 6 months, depending on whether automatic test equipment boards are reused or used for the first time. Additionally, the time delay may depend on the level of technology and the complexity of the qualified memories.
With respect to this relatively high effort, in many cases, the number of soft error rate samples employed for soft error rate testing is typically reduced to the minimal possible value, for example to 15 samples from three different lots. However, this may reduce the possibilities of performing a real soft error rate oriented design development. If the qualification of a particular integrated circuit for soft error rate fails, there may be a relatively high loss of time.
In view of the situation described above, the present disclosure provides apparatuses and methods wherein some or all of the above-mentioned issues may be overcome or at least reduced.